Three wire digital synchronizer

ABSTRACT

A three-wire digital synchronizer for use in an aircraft for synchronizing flight data to prevent an abrupt change in aircraft attitude when switching from manual to automatic control. Converting means are provided for converting the intermediate output of a three-wire signal device, such as a synchro, to pulses related in quantity to the actual flight of the aircraft. A counter/register counts the pulses and applies the count to a register until control of the aircraft is switched from manual to automatic control whereupon the count present in the register is locked in but the count in the counter/register continues to change in accordance with the flight data. A subtractor determines the difference in count contained in the counter/register and the register and the difference is used to automatically correct flight of the aircraft.

United States Patent EMBQWII l A.C. VOLTAG E SOURCE SAMPLING PU LSEGENERATOR 34 SELECTOR 6 COUNTER REGISTER e, REGISTER DIFFERENCE REGISTERCONTROL CIRCUIT Primary Examiner-Donald D. Forrer Assistant Examiner-B.P. Davis Attorneys-S. H Hartz and Plante, Arens, l-lartz, Smith &

Thompson ABSTRACT: A three-wire digital synchronizer for use in anaircraft for synchronizing flight data. to prevent an abrupt change inaircraft attitude when switching from manual to automatic control.Converting means are provided for converting the intermediate output ofa three-wire signal device, such as a synchro, to pulses related inquantity to the actual flight of the aircraft. A counter/register countsthe pulses and applies the count to a register until control of theaircraft is switched from manual to automatic control whereupon thecount present in the register is locked in but the count in thecounter/register continues to change in accordance with the flight data.A subtractor determines the difference in count contained in thecounter/register and the register and the difference is used toautomatically correct flight of the aircraft.

SYSTEM READOUT DEVICE PATENTEUDECZ'I 197a SHEET Q 0F 6 THREE WIREDIGITAL SYNCIIRONIZER BACKGROUND OF THE INVENTION 1. Field of theInvention This invention relates to synchronizers for synchronizingautomatic control flight data with current flight data and, moreparticularly, to a digital synchronizer for use with threewire signaldevices, such as synchros.

2. Description of the Prior Art Electromechanical devices were usedheretofore for synchronizing flight data but these devices haddisadvantages with regard to weight, space, power and reliability.

In order to overcome these disadvantages, solid state digitalsynchronizers were developed but they are subject to ambiguities unlessthe range is limited. Also, the synchronizers are used heretofore werelinear over only a small range because the output was proportional tothe sine of the difference in the angle of the synchro corresponding toactual flight data and the angle of the synchro when automatic flightcontrol was effective. The present invention has all the advantages ofthe solid state digital synchronizer yet is not limited in range toavoid ambiguities and the output is linear over the entire range.

SUMMARY OF THE INVENTION The present invention uses a three-wire digitalsynchronizer for synchronizing flight data of an aircraft while theaircraft is flown manually. A selector controls a sampling circuit forselecting an intermediate output of a signal device providing threeoutputs corresponding to the aircraft's actual flight condition. A holdcircuit converts the output of the sampling circuit to a DC voltage andapplies the DC voltage to a detector which provides timing pulsesrelated in number to the actual flight condition. A counter/registercounts the timing pulses and applies the count to a register duringmanual control of the aircraft. When control of the aircraft is switchedto the automatic mode, the count is locked in the register to providereference flight data. The outputs of the counter/register and theregister are applied to a serial subtractor. The serial subtractordetermines the difference between the two counts and the difference isstored in a second register. The second register output is applied to anindicator and to a digital-toanalog converter for controlling theautomatic flight of the aircraft.

One object of the invention is to provide a smooth transition frommanual control of the aircraft to automatic control using digitaltechniques.

Another object of the invention is to convert three-wire synchro data todigital form.

Another object of the invention is to provide an electronic synchronizerhaving less size and weight, requiring less power, and having increasedreliability relation to electromechanical synchronizers.

Another object of the invention is to provide a solid state synchronizerwith unlimited range.

Another object of the invention is to provide an error voltage linearlyrelated throughout the entire range to the difference between an anglecorresponding to actual flight of the aircraft and an anglecorresponding to a reference flight.

The foregoing and other objects and advantages of the invention willappear more fully hereinafter from a consideration of the detaileddescription which follows, taken together with the accompanying drawingswherein one embodiment of the invention is illustrated by way ofexample. It is to be expressly understood, however, that the drawingsare for illustration purposes only and are not to be construed asdefining the limits ofthe invention.

DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram showing oneembodiment of a synchronizer constructed in accordance with the presentinvention.

FIGS. 2, 3 and 4 are schematic diagrams of the selector, sampling meansand detector, respectively, shown in FIG. I.

FIG. 5 is a graph showing the three outputs of a synchro including theintermediate output.

FIG. 6A shows the output of the detector shown in detail in FIG. 4.

FIG. 6B shows the relationship between the excitation voltage and theoutput of the hold circuit shown in FIG. I.

DESCRIPTION OF THE INVENTION Referring to FIG. I, an AC voltage source Isupplies sinusoidal voltages of one phase at terminals 8 and 9 and ofopposite phase at terminal I8 and square wave voltages at terminals IIand I4 having frequencies differing in accordance with a ratio of 5l2:l. Source I is grounded at terminal 5. The frequency of thesinusoidal voltage and of the lesser frequency square wave preferablyare the same for convenience. Output terminal 8 of source I is connectedto one end of a rotor winding I8 of a signal device 20 and to a terminal21 of a detector 22. The opposite end of the rotor win-ding I8 isconnected to ground. Signal device 20 is a conventional type synchrowith stator windings 23, 24 and 25 having a common connection to ground.

Stator windings 23, 24 and 25 are connected to terminals 28, 35 and 38of a sampling means 30 and to terminals 32, of an operation rangeselector 34.

A sampling pulse generator 43 of conventional type is connected toterminal 9 of source I and generates sampling pulses coincident with thepositive peak amplitudes of the sinusoidal voltage appearing onterminals 8 and 9 of source I. The sampling pulses from generator 43 areapplied to a terminal 45 of sampling means 30 and to a terminal 46 ofselector 34.

Terminal 18 of source I is connected to a terminal 47 of de' tector 22.Terminal II of source 1 is connected to a terminal 48 of detector 22 anda terminal 58 of a control circuit 52. Terminal 14 of source I isconnected to a terminal 54 of detector 22 and to a terminal 55 ofcontrol circuit 52.

An output terminal 58 of selector 34 is connected to a terminal 59 ofsampling means 30 and to a terminal 62 of control circuit 52.

An output terminal 68 of sampling means 30 is connected to an input of ahold circuit 70. The hold circuit 70 may be of a conventional type. Theoutput of hold circuit 70 is connected to a terminal 71 of detector 22.An output terminal 74 of control circuit 52 is connected to a terminal75 of a counter/register 77. An output terminal 79 of control circuit 52is connected to a terminal 80 of the counter/register 77, to a terminal81 of register 83, and a terminal 88 of a serial subtractor 89. An inputterminal 84 of control circuit 52 is connected to a terminal 85 of adifference register 86.

Counter/register 77 is a 10 stage conventional counterlregister capableof being preset to a specific value and being counted up or down uponcommand from the control circuit 52. Registers 83 and 86 areconventional 10 stage registers. Serial subtractor 89 is a conventionalsubtractor as described at page 341 of Pulse, Digital, and SwitchingWaveforms" by J. Millman and H. Taub, McGraw Hill Book Company (1965),for subtracting one binary word from another binary word.

An output terminal 91 of detector 212 is connected to a ter minal 92 ofcounter/register 77. An output terminal 941, representing outputterminals of each stage of the counter/register 77, is connected to aninput terminal 95 representing input terminals of each stage of register86 and to input terminal 96 representing input terminals of each stageof register 83. An output terminal 98 of the output stage of thecounter/register 77 is connected to an input terminal 99 of thesubtractor 89. An output terminal I02 of the subtractor 89 is connectedto an input terminal I83 of an input stage of the counter/register 77. Aterminal of an output stage of register 83 is connected to an inputterminal III of an input stage of register 83, providing forrecirculation of the registers contents, and to an input terminal lI2 ofthe subtractor 89. A terminal IIS representing output terminals of eachstage of register 86 is connected to a readout device I20 and to a firstinput of a conventional digital-to-analog converter .high-logic level DCvoltage or a low-logic level DC voltage, is

connected to a terminal 126 of register 83.

Referring to FIG. 2, terminal 32 of the selector 34 is connected topositive input terminals of comparators 200, 202 and 203. The terminal36 is connected to a negative input terminal of comparator 200, and topositive input terminals of comparators 205 and 206. Terminal 39 isconnected to negative input terminals of comparators 202 and 205 and toa positive input terminal of a comparator 208. Negative input terminalsof comparators 203, 206 and 208 are connected to ground.

Terminal 46 of selector 34 is connected to NAND-gates 209, 210, 212,214, 216, 217, 220, 221, 223, 224, 226 and 228. Comparators 200, 202,203, 205, 206 and 208 each have a first output that is grounded.Comparator 200 has a second output connected to an inverter 229 and toNAND-gate 210 whose output is applied to a NOT-OR gate 230. The outputof inverter 229 is connected to NAND-gate 209 whose output is applied toa NOT-OR gate 231. A second output of comparator 202 is connected to aninverter 233 and to NAND-gate 214 whose output is applied to a NOT-ORgate 234. The output of inverter 233 is connected to NAND-gate 212 whoseoutput is applied to a NOT-OR gate 235. A second output of comparator205 is connected to an inverter 237 and to NAND-gate 217 whose output isapplied to a NOT-OR-gate 238. The output of inverter 237 is connected toNAND-gate 216 whose output is applied to a NOT-OR gate 239. A secondoutput of comparator 203 is connected to an inverter 242 and toNAND-gate 221 whose output is applied to a NOT-OR gate 243. The outputof inverter 242 is connected to NAND-gate 220 whose output is applied toa NOT-OR gate 244. A second output of comparator 208 is connected to aninverter 248 and to NAND-gate 224 whose output is applied to a NOT-ORgate 249. The output of inverter 248 is connected to NAND-gate 223 whoseoutput is applied to a NOT-OR gate 250. A second output of comparator206 is connected to an inverter 253 and to NAND-gate 228 whose output isapplied to a NOT-R gate 254. The output of inverter 253 is connected toNAND-gate 226 whose output is applied to NOT-OR gate 255.

The output of NOT-OR gate 231 is connected to NOT-OR gate 230 and toNAND-gates 263, 264, 266, 267, 269 and 270. The output of NOT-OR gate230 is connected to an input of NOT OR gate 231 and to NAND-gates 271,273, 275,276, 278 and 279. The output of NOT-0R gate 235 is connected toan input to NOT-OR gate 234 and to NAND-gates 266, 267, 269, 270, 271,and 273. The output of NOT-OR gate 234 is connected to an input toNOR-OR gate 235 and to NAND- gates 263, 264, 275, 276, 278 and 279. Theoutput of NOT- OR gate 239 is connected to an input to NOT-OR gate 238and to NAND-gates 269, 270, 271, 273, 275 and 276. NOT- OR gate 238output is connected to an input of NOT-OR gate 239 and to NAND-gates263, 264, 266, 267, 278 and 279. NOT-OR gate 244 output is connected toan input of NOT- OR gate 243 and to NAND-gates 263 and 273. The outputof NOT-OR gate 243 is connected to an input of NOT-OR gate 244 and toNAND-gates 264 and 271. The output of NOR-OR gate 250 is connected to aninput of NOT-OR gate 249 and to NAND-gates 267 and 276. The output ofNOTOR gate 249 is connected to an input of NOT-OR gate 250 and to NAND-gates 266 and 275. The output of NOT-OR gate 255 is connected to aninput of NOT-OR gate 254 and to NAND-gates 269 and 279. The output ofNOT-OR gate 254 is connected to an input of NOT-OR gate 255 and toNAND-gates 270 and 278.

Conductors 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311 and 312are connected to outputs of NAND-gates 271, 275, 276, 279, 278, 264,263, 267, 266, 270, 269 and 273, respectively. Conductors 301 through312 interconnect the selector 34 with the sampling means 30 throughterminals 58 and 59, respectively.

Referring to FIG. 3, the sampling means 30 is composed of threeidentical sampling circuits indicated as 30A, 30B and 30C. In circuit30A, conductors 301, 306, 307 and 312 from the selector 34 of FIG. 2 areconnected to inputs of a NOT-OR gate 350. The output of NOT-OR gate 350is connected toan input of a NAND-gate 353. Terminal 45 is connected toa .second input of NAND-gate 353. The output of NAND-gate 353 isconnected to an inverter 355 whose output is connected to a samplingnetwork 360. Sampling network 360 is a conventional circuit which may beof a type similar to a network manufactured by the Amelco Corporationand having their part number sl209. Terminal 28 is connected to samplingnetwork 360. The output of network 360is connected to terminal 68.

Circuits 30B and 30C are the same as circuits 30A. Conductors 304, 305,310 and 311 from selector 34 of FIG. 2 are connected to circuit 308.Conductors 302, 303, 308 and 309 from selector 34 of FIG. 2 areconnected to circuit 30C. Terminal 45 also is connected to circuits 30Band 30C. The outputs of circuits 30B and 30C are connected to tenninal68.

Referring to FIG. 4, detector 22 has terminal 21 connected to a positiveterminal of a comparator 401. Terminal 71 is connected to a negativeterminal of comparator 401 and to a positive terminal of a comparator404 and a negative terminal of a comparator 407. Terminal 47 isconnected to a negative terminal of comparator 404. A positive terminalof comparator 407 is connected to ground. First output terminals ofcomparators 401, 404 and 407 are connected to ground.

A second output terminal of comparator 401 is connected to a NAND-gate413. A second output terminal of comparator 404 is connected to aNAND-gate 420. A second output of comparator 407 is connected to aninverter 421 and to NAND-gate 420. The output of inverter 421 isconnected to NAND-gate 413. Terminals 48 and 54 are connected toNAND-gates 413 and 420 and the outputs of the NAND gates are connectedto a NOT-0R gate 422. The output of NOT-OR gate 422 is connected toterminal 91.

DESCRIPTION OF OPERATION Referring to FIG. 1, source 1 applies a 400hertz sinusoidal excitation voltage to the rotor winding 18 of thesignal device 20 and to tenninal 21 of the detector 22. The signaldevice 20 transforms the excitation voltage into three 400 hertz outputsacross stator windings 23, 24 and 25. The amplitude of each outputvaries as a function of the sine of the shaft angle of the signal device20 which is related to the actual flight of the aircraft. The three saidfunctions of the sine of the shaft angle of the signal device 20 areshaft angle degrees out of phase with each other.

Referring to FIG. 5, the outputs of stator windings 23, 24 and 25 ofsignal device 20 are represented by the waveforms A, B and C,respectively. It should be noted that these waveforms representenvelopes of the three 400 hertz sinusoidal outputs of the signal device20. As the shaft of signal device 20 is rotated through 360, eachwaveform completes one cycle. In FIG. 5 the 360 are divided into 12 30segments 1 through 12' to avoid ambiguities in the output of thesynchronizer. The segments are determinable from the followingconditions: A B, A C, B C, A 0, B 0, and C 0. For example, a angularshaft displacement lies in segment 6, the conditions that define thatsegment are A B, A C, B C and A 0. The condition for all the segments 1'through 12' are shown in table 1 below.

TAB LE 1 Synchro out put sam plvd Table l -Continued AND gate havingnegative Sampling Syncln-o bogpulsev circuit output ment Conditlomoutput enabled Sampled A B,A C,B C,B 0 270 30A A 11' .4 A B,A C,B C, B 0260 30A A 12 A B, A C, B C, A 0 273 308 B Table l indicates which NANDgate in selector 34, as shown in FIG. 2, provides the negative pulseoutput; the segment meeting the conditions imposed by the relationshipof the signal device outputs; and the enabled sampling circuit insampling means 30.

In FIG. 2, selector 34 receives the outputs of the signal device 20 andsampling pulses from the pulse generator 43. Selector 34 has 12 DCoutputs, each output corresponding to one of the segments shown in FIG.5. When the shaft of the signal device 20 is displaced through an angle0, one NAND gate corresponding to the segnent in which angle 0 lies willhave negative output pulses coinciding with the sampling pulses fromgenerator 43 while the other I l NAND gate outputs will be at a high-DCvoltage level.

For example, with the shaft of the signal device 20 displaced to anangle of 160, the intermediate output is across stator winding 23 and isshown by waveform A in FIG. 5. The conditions, as previously stated, areA B, or the voltage on terminal 36 is more positive than the voltage onterminal 32 in FIG. 2; A C, or the voltage on terminal 32 is morepositive than the voltage on terminal 39; B C, or the voltage onterminal 36 is more positive than the voltage on terminal 39; and A 0,or the voltage on terminal 32 is positive with respect to ground.Comparators 202, 203 and 205 will have high-level DC outputs whilecomparator 200 will have a low-level DC output enabling NAND-gates 209,214, 217 and 221. Sampling pulses from the generator 43 appearing onterminal 46 will pass through and be inverted by those NAND gates. Thenegative output pulses of NAND-gates 209, 214, 217 and 221 are invertedby NOT-OR gates 231, 234, 238 and 243 and applied to NAND-gate 264causing said gate to have negative output pulses which are applied toconductor 306.

The selector 34 negative output pulses will activate a sampling circuitA, 3013 or 30C of the sampling means 30 as shown in FIG. 3 as a functionof outputs A, B or C from signal device 20 depending on which is anintermediate output with respect to the other outputs. Returning to theexample, the negative pulses on conductor 306 are inverted by NOT-ORgate 350 and applied to NAND-gate 353 simultaneously with the samplingpulses appearing on terminal 45. The negative output pulses of NAND-gate353 are inverted by inverter 355 and applied to the sampling network360. Each sampling pulse on terminal causes sampling network 360 to passto terminal 68 a pulse corresponding to the peak amplitude of the outputfrom stator winding 23 since the output from stator winding 23 is theintermediate output from signal device 20.

The hold circuit receives the pulse output of sampling means 30 andprovides a DC voltage which varies as a function of the sine of theangular displacement of the shaft of the signal device 20, as shown inFIG. 5.

Detector 22 receives the DC output of hold circuit 70 and sinusoidal andsquare wave outputs from source I and provides, at its output terminal91, a series of pulses related in time to the square wave outputs ofsource 1 and corresponding in quantity to the relationship of the DCoutput of hold circuit 70 and the sinusoidal outputs of source 1.

Referring to FIG. 4, comparator 401 of detector 22 compares the 400hertz sine wave 0 reference appearing on terminal 21 to the DC output ofthe hold circuit 70 appearing on terminal 71. The 400 hertz sinusoidalvoltage, 180 out of phase, present on terminal 47 of detector 22 iscompared to the output voltage of the hold circuit 70 by comparator 404.Comparator 407 compares a ground reference to the DC output of the holdcircuit 70 present at terminal 71. At an angle of displacement of 160,the output of the hold circuit 70 is greater than ground reference.

Comparators 401 and 407 will each pass a pulse, during the positiveportion of the cycle, whose width is controlled by the level of the holdcircuit 70 DC output as shown in FIG. 6. The pulses do not occurtogether due to the I phase difference between the voltages at terminals21 and 47. At an angle of 160, the pulse from comparator 402 partiallyenables NAND- gate 413. Comparator 407 has a low-level DC output sincethe voltage at terminal 71 from the hold circuit 70 is positive withrespect to ground and that output disables NAND-gate 420. The output ofcomparator 407 is inverted to a high-level DC voltage by inverter 421and applied to NAND-gate 413 fully enabling it along with the output ofcomparator 401.

Coincidence of the positive portions of the 400 hertz square wave atterminal 40 and the 204.8 kilohertz square wave at terminal 54 ofdetector 22 causes the enabled NAND-gate 413 to provide a maximum of 256pulses for one cycle of the 400 hertz square wave.

The determination of the maximum pulse count of 256 pulses per cycle ofthe 400 hertz sinusoidal wave is computed as follows:

Referring to FIG. 6A the actual time duration of the output of detector22 is a function of the angle 0 and since the output is in the form oftiming pulses, the quantity of timing pulses is a function of the angle6. By way of example, comparator 401 in the detector 22 will have anoutput when the 400 hertz sinusoidal voltage exceeds the level of theoutput from the hold circuit 70 as shown in FIG. 6B. This occurs after atime interval The pulse is terminated when the 400 hertz voltagediminishes to a value less than the output of the hold circuit 70 andits width is the time interval The remaining time interval of the halfcycle is t The time for the half cycle is T, therefore:

T=t,+t +t and (I Due to the symmetry of the sinusoidal voltage t,=t and(2) equation (I) may be rewritten as T=2t +t or (3) t,=1/2 (T (4) l Theequation for the output voltage of the hold circuit may be written as IGV sin 0 (5) Where V is the peak voltage present at terminal 8 of source1, and 6 is the angle of displacement of the rotor winding 18 of thesignal device 20. The sinusoidal voltage is equal to the output of thehold circuit 70 at the end of the time interval t,. It follows that sin0=sin w t, or (6) 0=w t, (7) where m is the frequency of the voltagepresent at terminal 8 of source 1. Substituting the value for t, that isshown in equation (4), equation (7) can be written as 6=wl2 (Tt or (8) t=T-2/w0. (9) By definition w=21r f (10) wherefis the reciprocal of theperiod of the wave. Thus equation l0) may be written as w=21r/2T= rr/Tand substituting equation (ll) into equation (8) and rewriting,

0=1r/21r/2n/T 12 t =T2 T/1r 0. (13) However 2, Tand n are constants sothat I K -IQ 6. (14) Equation (l4) shows that the pulse width varies asa function of the variable 0 and hence the quantity of timing pulsescontained in the output of detector 22 is a function of 0.

However, in use the output of hold circuit 70 is not allowed to exceedV/2 since it is dependent on the intermediate output of the signalsource 20 while the sinusoidal voltage maximum amplitude is V.Therefore, equation 14, as applied to the detector 22, is only requiredto be valid within the range of the hold circuit 70 output for 0 0 s 30and Be. I80". Counter/register 77 is preset to the proper value andcounting direction in order to account for the constant K and the signof K, from equation (14), as well as to allow for the relative phaseshift and ambiguities present in the outputs of the signal device 20sampled one at a time.

The present digital synchronizer has an accuracy of 10 bits.Mathematically the accuracy is stated as 2 bits=360=1,024 bits orlbit=0.35l4 (16) Referring to equation (12), the counting rate is thecoefficient 1r/2T 1r/2=90=% of full counb256 bits (17) T=ll800 sec. (18)fclock =256X800=204.8 kHz. (19) Hence to develop the 1,024 bit accuracy,the NAND gates are gated by the 400 hertz square wave and the 204.8kilohertz square wave. The ratio of 204.8 kilohertz to 400 kilohertz is512. However, comparator 401 or 404 pulse output will only occur duringone half of a cycle of the 400 hertz per excitation signal. Therefore,the maximum number of bits that can occur is 256 bits. A bit is equal toone pulse from detector 22.

Referring to FIG. 1, counter/register 77 provides two functions; itcounts the output of detector 22 and transfers the count to the serialsubtractor 89, and it accepts the difference from the subtractor 89 forparallel transfer of the difference to register 86. Counter/register 77receives, from control circuit 52, a clearing pulse that resets thecounter/register 77 to zero prior to every count, a preset command thatsets the counter/register 77 to a count corresponding to an angle of 30,90, 150, 210, 270or 330and a high-level DC voltage up command or downcommand that causes the counter/register 77 to count up or count downfrom the preset count when it receives the pulse output from detector22. Control circuit 52 also provides shift pulses to counter/register 77for serial shifting its contents. Table 2 below relates the actualangular displacement of signal device and the operation range segment tothe preset angle and the counting sequence.

For purposes of illustration, assuming the angle 0 is 0, during thepositive portion of one cycle of the 400 hertz excitation voltage, 256pulses, representing 90, are applied to counter/register 77. Sincecounter/register has been preset to 256 and commanded to count down bythe control circuit 52, each pulse from detector 24 will decrease thecount in counter/register 77, until the count of 0 is reached.Counter/register 77 contains the count relating to actual flight.

Control circuit 52 receives the square wave outputs of source 1 atterminals 50 and 55, and the output of selector 34 at terminal 62representing a plurality of terminals. Control circuit 52 contains logiccircuitry for providing shift pulses to the counter/register 77,registers 83 and 86, and the subtractor 89, and provides inputs tocounter/register 77 for presetting it. Control circuit 52 also providesvoltages to counter/register 77 for controlling the counting sequence ofcounter/register 77.

Counter/register 77 applies its contents through a plurality ofconductors, one for each stage in counter/register 77, to register 83which will maintain the same contents as counter/register 77 prior to acommand from the command source 125.

After the command, the contents of counter/register 77 are preventedfrom entering register 83 and the contents that register 83 had at thetime of the command are recirculated and are thus locked in. Register 83output is used as a reference for developing error signals.

The contents of counter/register 77 and the contents of register 83 areapplied serially to the serial subtractor 89 through terminals 99 and112, respectively. Prior to receipt of a command from command source125, register 83 contains the same contents as counter/register 77 andthe output of the serial subtractor 89 is binary zero which is enteredinto counter/register 77 through terminals 102 and 103 of the subtractor89 and counter/register 77, respectively. When counter/register 77contains the resulting difference, the contents of counter/register 77is parallel applied to difference register 86, through terminals 94 and95, which applies the contents of register 86 to readout device and todigital-toanalog converter 122 whose analog output is applied to theaircraft control system 130.

Upon application of a low-level DC voltage, automatic control command,from command source 125 to register 83, the contents of counter/register77 are prevented from entering register 83. Subsequent changes in theangular shaft position of the signal device 20 results in a change ofthe contents of counter/register 77 as heretofore explained, butregister 83 will retain the same contents prior to the automatic controlcommand. Therefore, register 83 contains a reference count for theautomatic control of mode of operation, locked in, while the contents ofcounter/register 77 can vary.

The outputs of counter/register 77 and register 83 applied to the serialsubtractor 89 after the automatic control command from command source125 causes subtractor 89 to have a binary output representing thedifference between the contents of counter/register 77 and register 83,and the output is fed back to counter/register 77. While the differenceis being entered into counter/register 77, the detector 22 does not havean output. The counter/register 77 accepts the difference figure untilall bits of the binary word are in counter/register 77 at which time itparallel transfers the binary information to the difference register 86.Register 86 provides for temporary storage of the difference. Register86 applies the difference to readout device 120 or the analog-to-digitalconverter 122 whose output is applied to theaircraft control system forcorrecting aircraft flight until the difference contained in register 86is zero. Register 83 recirculates its contents through terminals 110 and111 so that after the subtraction by the subtractor 89, register 83 willhave the same contents it had prior to the subtraction. The necessarycorrection to aircraft flight is slight since just prior to theautomatic control command, the counter/register 77 and the register 83had the same counts.

In summary, the signal device 20 provides output signals related toactual flight of aircraft. The output signals are converted to a DCvoltage related to actual flight by sampling means 30 and hold circuit70. The DC voltage and outputs from source 1 cause detector 22 toprovide timing pulses whose quantity is related to the actual flight ofthe aircraft as indicated by the angular displacement of the signaldevice's 20 shaft. Counter/register 77 is preset to an angle and countsup or down from that angle under the control of control circuit 52.Register 83 will accept the contents of counter/register 77 until anautomatic control command from command source 125 causes register 83 tolock in the count present at the time of the command. The contents ofcounter/register 77 and register 83 are applied to subtractor 89 andsubtractor 89 obtains the difference between the two contents. Thedifference is serially entered in counter/register 77 until the completebinary information for the difference is in counter/register 77 at whichtime the difference is parallel transferred to register 86 which in turnapplies the difference to readout device 1.20 or to the aircraft controlsystem 130.

Although but a single embodiment of the invention has been illustratedand described in detail, it is to be expressly understood that theinvention is not limited thereto. Various changes may also be made inthe design and arrangement of the parts without departing from thespirit and scope of the invention as the same will now be understood bythose skilled in the art.

What is claimed is:

l. A synchronizer comprising a signal source providing three relatedoutputs corresponding to a condition, means for selecting anintermediate output, a detector connected to the selecting means andproviding pulses corresponding to the intermediate output,counter/register means connected to the detector for counting andregistering the pulses and providing two outputs, command means formaintaining both outputs at the same count when under manual control andfor maintaining one output constant in accordance with the conditionwhen changed from manual to automatic control while the other outputchanges in accordance with the present condition, and a subtractorconnected to both outputs of the counter/register means and providing anoutputvcorrespond' ing to the difference in the two outputs of thecounter/register means, the output from the subtractor corresponding tothe difference in the present condition from the condition at the timeof changing to automatic control.

2. A synchronizer as defined in claim 1 in which the selecting meansincludes a selector connected to the signal source, a sampling circuitconnected to each output of the signal source and controlled by theselector for sampling the positive peaks of the intermediate outputonly, and a holding circuit connected to the sampling circuits forproviding a DC voltage cor responding to the condition.

3. A synchronizer as defined in claim 1 in which the counter/registermeans includes a counter/register for counting pulses from the detectorand providing a first output corresponding thereto, and a registerconnected to the counter/register and receiving the count from thecounter/register until a command from the command means coincident tothe change from manual control to automatic control causes the registerto hold the count at the time of the command and providing a secondoutput corresponding thereto while the count of the counter/registerchanges in accordance with changes in the condition.

4. A synchronizer as defined in claim 1 further comprising a registerresponsive to the output of the subtractor and providing temporarystorage of the difference output of the subtrac tor.

5. A synchronizer as defined in claim 1 further comprising means forproviding timing pulses and AC voltages of opposite phases and in whichthe detector includes means for comparing the output of the selectingmeans with a ground reference to determine polarity of the selectingmeans output and to provide pulses of a width corresponding to theintermediate output, and switching means connected to the comparingmeans and passing timing pulses corresponding in number to the pulsewidth and to the intermediate output of the signal source.

6. A synchronizer as defined in claim 5 in which the comparing meansincludes a first comparator for comparing the output of the selectingmeans with one AC voltage and providing pulses of a width correspondingthereto, a second comparator for comparing the output of the selectingmeans with the other AC voltage of opposite phase and providing pulsesof a width corresponding thereto, and a third comparator for comparingthe output of the selecting means with the ground reference andproviding-an output corresponding thereto, and in which the switchingmeans includes an inverter connected to the third comparator, a firstNAND gate connected to the first comparator and to the inverter, asecond NAND gate connected to the second and third comparators, thefirst NAND gate being controlled by the output of the first comparatorand the inverter and the second NAND gate being controlled by the outputof the second and third comparators so that one of the NAND gates passestiming pulses corresponding in number to the pulse width and to theintermediate outlput of the si nal source.

7. A sync ronlzer as efined in claim 2m which the selector includesfirst, second and third comparators connected in different combinationsto two of the three outputs from the signal source and providing outputscorresponding to the relative amplitudes of the three outputs from thesignal source; fourth, fifth and sixth comparators each connected to anout put of the signal source and to a ground reference and thecomparators providing outputs corresponding to the relative amplitude ofthe three outputs with respect to the ground reference; an inverterconnected to the output of each comparator; and a plurality of NANDgates connected in different combinations to the inverters andcomparators and providing an output corresponding to the intermediateoutput and to the condition.

8. A synchronizer as defined in claim 2 further comprising a pulsegenerator connected to the selector and to the sampling circuits andproviding pulses coincident with positive peaks of the outputs of thesignal source so that the sampling circuits sample the positive peaks ofthe intermediate output of the signal source.

UNITED STATES PATENT OFFICE CE'NFICATE 0F CUREC'NUN 3, 9,7 DatedDecember 21, 1971 Patent No.

John C. Strole, et a1 Inventor(s) It is certified that error appears inthe above-identified patent and that said Letters Patent are herebycorrected as shown below:

On the cover sheet, the 'co-inventor "Morelines" should read Moraine:

Signed and sealed this 17th day of October 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Commissioner of PatentsAttesting Officer FORM PC4050 (10'69) USCOMM-DC 60376-P69 U.5iGOVERNMENT PRINTING OFFICE 2 IDID O35B-334,

1. A synchronizer comprising a signal source providing three relatedoutputs corresponding to a condition, means for selecting anintermediate output, a detector connected to the selecting means andproviding pulses corresponding to the intermediate output,counter/register means connected to the detector for counting andregistering the pulses and providing two outputs, command means formaintaining both outputs at the same count when under manual control andfor maintaining one output constant in accordance with the conditionwhen changed from manual to automatic control while the other outputchanges in accordance with the present condition, and a subtractorconnected to both outputs of the counter/register means and providing anoutput corresponding to the diffErence in the two outputs of thecounter/register means, the output from the subtractor corresponding tothe difference in the present condition from the condition at the timeof changing to automatic control.
 2. A synchronizer as defined in claim1 in which the selecting means includes a selector connected to thesignal source, a sampling circuit connected to each output of the signalsource and controlled by the selector for sampling the positive peaks ofthe intermediate output only, and a holding circuit connected to thesampling circuits for providing a DC voltage corresponding to thecondition.
 3. A synchronizer as defined in claim 1 in which thecounter/register means includes a counter/register for counting pulsesfrom the detector and providing a first output corresponding thereto,and a register connected to the counter/register and receiving the countfrom the counter/register until a command from the command meanscoincident to the change from manual control to automatic control causesthe register to hold the count at the time of the command and providinga second output corresponding thereto while the count of thecounter/register changes in accordance with changes in the condition. 4.A synchronizer as defined in claim 1 further comprising a registerresponsive to the output of the subtractor and providing temporarystorage of the difference output of the subtractor.
 5. A synchronizer asdefined in claim 1 further comprising means for providing timing pulsesand AC voltages of opposite phases and in which the detector includesmeans for comparing the output of the selecting means with a groundreference to determine polarity of the selecting means output and toprovide pulses of a width corresponding to the intermediate output, andswitching means connected to the comparing means and passing timingpulses corresponding in number to the pulse width and to theintermediate output of the signal source.
 6. A synchronizer as definedin claim 5 in which the comparing means includes a first comparator forcomparing the output of the selecting means with one AC voltage andproviding pulses of a width corresponding thereto, a second comparatorfor comparing the output of the selecting means with the other ACvoltage of opposite phase and providing pulses of a width correspondingthereto, and a third comparator for comparing the output of theselecting means with the ground reference and providing an outputcorresponding thereto, and in which the switching means includes aninverter connected to the third comparator, a first NAND gate connectedto the first comparator and to the inverter, a second NAND gateconnected to the second and third comparators, the first NAND gate beingcontrolled by the output of the first comparator and the inverter andthe second NAND gate being controlled by the output of the second andthird comparators so that one of the NAND gates passes timing pulsescorresponding in number to the pulse width and to the intermediateoutput of the signal source.
 7. A synchronizer as defined in claim 2 inwhich the selector includes first, second and third comparatorsconnected in different combinations to two of the three outputs from thesignal source and providing outputs corresponding to the relativeamplitudes of the three outputs from the signal source; fourth, fifthand sixth comparators each connected to an output of the signal sourceand to a ground reference and the comparators providing outputscorresponding to the relative amplitude of the three outputs withrespect to the ground reference; an inverter connected to the output ofeach comparator; and a plurality of NAND gates connected in differentcombinations to the inverters and comparators and providing an outputcorresponding to the intermediate output and to the condition.
 8. Asynchronizer as defined in claim 2 further comprising a pulse generatorconnected to the selector and to the sampling circuits and providingpulses coincident with positive Peaks of the outputs of the signalsource so that the sampling circuits sample the positive peaks of theintermediate output of the signal source.